... criteria is the presence of orientation marks within the boundary of board. These marks could be the board reference so long as it cannot | MULTILAYER CIRCUITS | be read from the other side. (This is for your protection to prevent the boards made inside out). Images should comply with design rules that | MULTILAYER CIRCUITS | will result in a board that will meet performance and cost requirements. - Scale must be given, tapes securely stuck to the backing sheet, track | MULTILAYER CIRCUITS | to pad & track to track joints complete and the backing sheet clean. - Scale must be given and be at least 2:1. Plots must | MULTILAYER CIRCUITS | also offer sharp edge definition and traces dense enough for blocking light when photographing. - Preferred on 7mil (178mm) thick base for stability. Films should | MULTILAYER CIRCUITS | be plotted on laser photoplotter or on vector photoplotter using a minimum resolution of ½mil (13mm). - Preferred in Gerber® format although accepted in other | MULTILAYER CIRCUITS | formats. (Refer to CID-014 for information on Documentation in Digital Form). - files are the only acceptable form of ...
[ Multilayer Circuits ]


... Drawings must be supplied with each new job and should contain the following information to ensure that the finished board is to your requirements. | MULTILAYER CIRCUITS | - Always required even when a drill file is supplied, to enable inspection of panels immediately after drilling and finished boards prior to despatching. Hole | MULTILAYER CIRCUITS | sizes must be clearly represented with distinct differences between each size. Tolerances are not required unless different to our standard of +0.1 / -0.05 mm. | MULTILAYER CIRCUITS | - Preferred with overall mechanical dimensions including notches, cutouts and slots. Also preferred is a positioning (datum) dimension (drilled hole is best). Tolerances are not | MULTILAYER CIRCUITS | required unless different to our standard of + / -0.25 mm. Other information required for all boards includes: board thickness (standard = 1.6mm) base copper | MULTILAYER CIRCUITS | thickness (std = 18mm) solder mask colour (std = green) solder mask type (std = liquid photoimageable) component legend colour (std = white) bare board | MULTILAYER CIRCUITS | testing requirement (std for multilayer ...
[ Multilayer Circuits ]


... fabricators have theirs. Checks and balances can resolve any conflicts between the two. | TAKE SOLDERMASK LAYERS |, for instance. Often, these layers are | MULTILAYER CIRCUITS | not "intelligent" layers within a CAD tool; that is, there is not much in the way of capability checking within the tool. As a result, | MULTILAYER CIRCUITS | these are among the more troublesome layers for fabricators. The solution here is a fabrication analysis tool that can handle such issues as clearances, coverage, | MULTILAYER CIRCUITS | webbing, and so forth. For instance, most fab shops want the largest possible | CLEARANCES | in a solder layer so that mask doesn't end | MULTILAYER CIRCUITS | up on pads. On the flip side, copper is not supposed to be exposed. The two requirements - no mask on pads and unwanted exposed | MULTILAYER CIRCUITS | copper - must be balanced. It is not easy to do. How can the designer help? Devise a standardized clearance, or set the clearances at | MULTILAYER CIRCUITS | 1:1, and let the shop do the soldermask enhancement. Here's another issue: | THE SOLDERMASK | webbing between pads on fine-pitch surface mount ...
[ Multilayer Circuits ]